1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more specifically, to a method for forming a dielectric layer between gates in a flash memory device.
2. Discussion of Related Art
Programming and erasing operations in a flash memory device are accomplished by storing or erasing charges in or from a floating gate. The programming and erasing properties are dependent on the coupling ratio between the floating gate and the control gate. It is thus necessary to form a dielectric layer between the floating gate and the control gate in a uniform thickness.
A conventional method for manufacturing a flash memory device will be described with reference to FIG. 1.
A gate pattern G consisting of a tunnel oxide film 11, a floating gate 12, an ONO dielectric layer 13 and a control gate 14 is formed on a semiconductor substrate 10. An impurity is doped into the semiconductor substrate 10 to form source/drain 15. The floating gate 12 is formed using a doped silicon film and the ONO dielectric layer 13 is formed by stacking a lower oxide film ONO1, a nitride film ONO2 and an upper oxide film ONO3.
If the flash memory device is fabricated by means of the aforementioned method, the floating gate 12 and the lower oxide film ONO1 formed of silicon react each other in the annealing process. Accordingly, re-oxidization occurs, which results in a thick lower oxide film ONO1. For example, a thickness “t1” of the lower oxide film ONO1 before the annealing process is increased to a thickness of “t2”. Such re-oxidization is more active at the edges of the lower oxide film ONO1, resulting in the bird's beak that the edges are relatively thick. As the thickness of the lower oxide film ONO1 is increased, the coupling ratio between the floating gate 12 and the control gate 14 is lowered. Moreover, since the thickness of the lower oxide film ONO1 is not uniformly increased over the entire wafer, there is a problem that the yield is lowered due to increased dispersion of the threshold voltage at the time of the programming and erasing operations of the device.